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flash memory k8s6415et(b)b revision 1.1 january, 2006 1 document title 64m bit (4m x16) muxed burs t , multi bank nor flash memory revision history revision no. 0.0 1.0 1.1 remark history initial issue revision - specification finalized - add the requirement and note of quadruple word program operation bottom boot block description is added draft date october 20, 2004 march 22, 2005 january 09,2006
flash memory k8s6415et(b)b revision 1.1 january, 2006 2 64m bit (4m x16) muxed burs t , multi bank nor flash memory the k8s6415e featuring single 1.8v power supply is a 64mbit muxed burst multi bank flas h memory organized as 4mbx16. the memory architecture of t he device is designed to divide its memory arrays into 135 blocks with independent hardware pro- tection. this block architecture provides highly flexible erase and program capability. the k8s6415e nor flash consists of sixteen banks. this device is capable of reading data from one bank while programming or erasing in the other bank. regarding read access time, t he k8s6415e provides an 14.5ns burst access time and an 90ns initial access time at 54mhz. at 66mhz, the k8s6415e provides an 11ns burst access time and 70ns initial access time. the device performs a program opera- tion in units of single 16 bits (word) and an erase operation in units of a block. single or multiple blocks can be erased. the block erase operation is completed within typically 0.7 sec. the device requires 15ma as program/erase current in the extended temperature ranges. the k8s6415e nor flash memory is created by using sam- sung's advanced cmos process technology. this device is available in 44 ball fbga package. features general description samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin description pin name pin function a16 - a21 address inputs a/dq0 - a/dq15 multiplexed address/data input/output ce chip enable oe output enable reset hardware reset pin v pp accelerates programming we write enable wp hardware write protection input clk clock rdy ready output avd address valid input vcc power supply v ss ground ? single voltage, 1.7v to 1.95v for read and write operations ? organization - 4,194,304 x 16 bit ( word mode only) ? multiplexed data and address for reduction of interconnections - a/dq0 ~ a/dq15 ? read while program/erase operation ? multiple bank architecture - 16 banks (4mb partition) ? otp block : extra 256byte block ? read access time (@ c l =30pf) - asynchronous random access time : 90ns (54mhz) / 80ns (66mhz) - synchronous random access time : 88.5ns (54mhz) / 70ns (66mhz) - burst access time : 14.5ns (54mhz) / 11ns (66mhz) ? burst length : - continuous linear burst - linear burst : 8-word & 16-word with no-wrap & wrap ? block architecture - eight 4kword blocks and one hundreds twenty seven 32kword blocks - bank 0 contains eight 4 kword blocks and seven 32kword blocks - bank 1 ~ bank 15 cont ain one hundred twenty 32kword blocks ? reduce program time using the v pp ? support single & quad word accelerate program ? power consumption (typical value, c l =30pf) - burst access current : 30ma - program/erase current : 15ma - read while program/erase current : 40ma - standby mode/auto sleep mode : 15ua ? block protection/unprotection - using the software command sequence - last two boot blocks are protected by wp =v il - all blocks are protected by v pp =v il ? handshaking feature - provides host system with minimum latency by monitoring rdy ? erase suspend/resume ? program suspend/resume ? unlock bypass program/erase ? hardware reset (reset ) ? data polling and toggle bits - provides a software method of detecting the status of program or erase completion ? endurance 100k program/erase cycles minimum ? data retention : 10 years ? extended temperature : -25 c ~ 85 c ? support common flash memory interface ? low vcc write inhibit ? package : 44 - ball fbga type, 7.5x8.5mm 0.5 mm ball pitch 1.0 mm (max.) thickness
flash memory k8s6415et(b)b revision 1.1 january, 2006 3 44 ball fbga top view (ball down) functional block diagram rdy a21 v ss clk v cc we a16 a20 avd nc v ss a/dq7 a/dq6 a/dq13 a/dq12 a/dq3 a/dq15 a/dq14 v ss a/dq5 a/dq4 a/dq11 v cc reset v pp a19 a17 nc wp a18 ce v ss a/dq2 a/dq9 a/dq8 oe a/dq10 v cc a/dq1 a/dq0 12345678910 a c d b vcc vss ce oe we wp reset rdy a16~a21 a/dq15 interface & bank control x dec y dec latch & control latch & control dec x y dec erase control program control high voltage gen. bank 1 cell array bank 0 address bank 1 address bank 0 cell array avd a/dq0~ x dec y dec latch & control bank 15 cell array block inform vpp bank 15 address clk i/o
flash memory k8s6415et(b)b revision 1.1 january, 2006 4 table 2. k8s6415e device bank divisions bank 0 bank 1 ~ bank 15 mbit block sizes mbit block sizes 4 mbit eight 4kwords, seven 32kwords 60 mbit one hundred twenty 32kwords ordering information k 8 s 64 1 5 e t b - d e 7c samsung nor flash memory device type multiplexed burst density 64mbits operating temperature range c = commercial temp. (0 c to 70 c) e = extended temp. (-25 c to 85 c) block architecture t = top boot block, b = bottom boot block version 3rd generation access time refer to table 1 operating voltage range 1.7 v to 1.95v package f : fbga d : fbga(lead free) organization x16 organization table 1. product line-up k8s6415e synchronous/burst asynchronous speed option 7b (54mhz) 7c (66mhz) speed option 7b (54mhz) 7c (66mhz) v cc =1.7v-1.95v max. initial access time (t iaa, ns) 88.5 70 max access time (t aa, ns) 90 80 max. burst access time (t ba, ns) 14.5 11 max ce access time (t ce, ns) 90 80 max. oe access time (t oe, ns) 20 20 max oe access time (t oe, ns) 20 20
flash memory k8s6415et(b)b revision 1.1 january, 2006 5 table 3. block address table bank block block size (x16) address range bank0 ba134 4 kwords 3ff000h-3fffffh ba133 4 kwords 3fe000h-3fefffh ba132 4 kwords 3fd000h-3fdfffh ba131 4 kwords 3fc000h-3fcfffh ba130 4 kwords 3fb000h-3fbfffh ba129 4 kwords 3fa000h-3fafffh ba128 4 kwords 3f9000h-3f9fffh ba127 4 kwords 3f8000h-3f8fffh ba126 32 kwords 3f0000h-3f7fffh ba125 32 kwords 3e8000h-3effffh ba124 32 kwords 3e0000h-3e7fffh ba123 32 kwords 3d8000h-3dffffh ba122 32 kwords 3d0000h-3d7fffh ba121 32 kwords 3c8000h-3cffffh ba120 32 kwords 3c0000h-3c7fffh bank1 ba119 32 kwords 3b8000h-3bffffh ba118 32 kwords 3b0000h-3b7fffh ba117 32 kwords 3a8000h-3affffh ba116 32 kwords 3a0000h-3a7fffh ba115 32 kwords 398000h-39ffffh ba114 32 kwords 390000h-397fffh ba113 32 kwords 388000h-38ffffh ba112 32 kwords 380000h-387fffh bank2 ba111 32 kwords 378000h-37ffffh ba110 32 kwords 370000h-377fffh ba109 32 kwords 368000h-36ffffh ba108 32 kwords 360000h-367fffh ba107 32 kwords 358000h-35ffffh ba106 32 kwords 350000h-357fffh ba105 32 kwords 348000h-34ffffh ba104 32 kwords 340000h-347fffh bank3 ba103 32 kwords 338000h-33ffffh ba102 32 kwords 330000h-337fffh ba101 32 kwords 328000h-32ffffh ba100 32 kwords 320000h-327fffh ba99 32 kwords 318000h-31ffffh ba98 32 kwords 310000h-317fffh ba97 32 kwords 308000h-30ffffh ba96 32 kwords 300000h-307fffh bank4 ba95 32 kwords 2f8000h-2fffffh ba94 32 kwords 2f0000h-2f7fffh ba93 32 kwords 2e8000h-2effffh ba92 32 kwords 2e0000h-2e7fffh ba91 32 kwords 2d8000h-2dffffh ba90 32 kwords 2d0000h-2d7fffh ba89 32 kwords 2c8000h-2cffffh ba88 32 kwords 2c0000h-2c7fffh
flash memory k8s6415et(b)b revision 1.1 january, 2006 6 table 3. block address table (continued) bank block block size (x16) address range bank5 ba87 32 kwords 2b8000h-2bffffh ba86 32 kwords 2b0000h-2b7fffh ba85 32 kwords 2a8000h-2affffh ba84 32 kwords 2a0000h-2a7fffh ba83 32 kwords 298000h-29ffffh ba82 32 kwords 290000h-297fffh ba81 32 kwords 288000h-28ffffh ba80 32 kwords 280000h-287fffh bank6 ba79 32 kwords 278000h-27ffffh ba78 32 kwords 270000h-277fffh ba77 32 kwords 268000h-26ffffh ba76 32 kwords 260000h-267fffh ba75 32 kwords 258000h-25ffffh ba74 32 kwords 250000h-257fffh ba73 32 kwords 248000h-24ffffh ba72 32 kwords 240000h-247fffh bank7 ba71 32 kwords 238000h-23ffffh ba70 32 kwords 230000h-237fffh ba69 32 kwords 228000h-22ffffh ba68 32 kwords 220000h-227fffh ba67 32 kwords 218000h-21ffffh ba66 32 kwords 210000h-217fffh ba65 32 kwords 208000h-20ffffh ba64 32 kwords 200000h-207fffh bank8 ba63 32 kwords 1f8000h-1fffffh ba62 32 kwords 1f0000h-1f7fffh ba61 32 kwords 1e8000h-1effffh ba60 32 kwords 1e0000h-1e7fffh ba59 32 kwords 1d8000h-1dffffh ba58 32 kwords 1d0000h-1d7fffh ba57 32 kwords 1c8000h-1cffffh ba56 32 kwords 1c0000h-1c7fffh bank9 ba55 32 kwords 1b8000h-1bffffh ba54 32 kwords 1b0000h-1b7fffh ba53 32 kwords 1a8000h-1affffh ba52 32 kwords 1a0000h-1a7fffh ba51 32 kwords 198000h-19ffffh ba50 32 kwords 190000h-197fffh ba49 32 kwords 188000h-18ffffh ba48 32 kwords 180000h-187fffh bank10 ba47 32 kwords 178000h-17ffffh ba46 32 kwords 170000h-177fffh ba45 32 kwords 168000h-16ffffh ba44 32 kwords 160000h-167fffh ba43 32 kwords 158000h-15ffffh ba42 32 kwords 150000h-157fffh
flash memory k8s6415et(b)b revision 1.1 january, 2006 7 table 3. block address table (continued) bank block block size (x16) address range bank10 ba41 32 kwords 148000h-14ffffh ba40 32 kwords 140000h-147fffh bank11 ba39 32 kwords 138000h-13ffffh ba38 32 kwords 130000h-137fffh ba37 32 kwords 128000h-12ffffh ba36 32 kwords 120000h-127fffh ba35 32 kwords 118000h-11ffffh ba34 32 kwords 110000h-117fffh ba33 32 kwords 108000h-10ffffh ba32 32 kwords 100000h-107fffh bank12 ba31 32 kwords 0f8000h-0fffffh ba30 32 kwords 0f0000h-0f7fffh ba29 32 kwords 0e8000h-0effffh ba28 32 kwords 0e0000h-0e7fffh ba27 32 kwords 0d8000h-0dffffh ba26 32 kwords 0d0000h-0d7fffh ba25 32 kwords 0c8000h-0cffffh ba24 32 kwords 0c0000h-0c7fffh bank13 ba23 32 kwords 0b8000h-0bffffh ba21 32 kwords 0b0000h-0b7fffh ba21 32 kwords 0a8000h-0affffh ba20 32 kwords 0a0000h-0a7fffh ba19 32 kwords 098000h-09ffffh ba18 32 kwords 090000h-097fffh ba17 32 kwords 088000h-08ffffh ba16 32 kwords 080000h-087fffh bank14 ba15 32 kwords 078000h-07ffffh ba14 32 kwords 070000h-077fffh ba13 32 kwords 068000h-06ffffh ba12 32 kwords 060000h-067fffh ba11 32 kwords 058000h-05ffffh ba10 32 kwords 050000h-057fffh ba9 32 kwords 048000h-04ffffh ba8 32 kwords 040000h-047fffh bank15 ba7 32 kwords 038000h-03ffffh ba6 32 kwords 030000h-037fffh ba5 32 kwords 028000h-02ffffh ba4 32 kwords 020000h-027fffh ba3 32 kwords 018000h-01ffffh ba2 32 kwords 010000h-017fffh ba1 32 kwords 008000h-00ffffh ba0 32 kwords 000000h-007fffh after entering otp block, any issued addresses should be in the range of otp block address otp block address a21 ~ a8 block size (x16) address range 7fffh 128words 3fff80h-3fffffh table 3-1. otp block addresses
flash memory k8s6415et(b)b revision 1.1 january, 2006 8 table 4. device bus operations note : l=v il (low), h=v ih (high), x=don?t care. operation ce oe we a16-21 a/dq0-15 reset clk avd asynchronous read operation l l h add in add in/ d out hll write l h add in add in / d in hlx standby hxxxhigh-zhxx hardware reset xxxxhigh-zlxx load initial burst address l h h add in add in h burst read operation l l h x burst d out hh terminate burst read cycle via ce hxxxhigh-zhxx terminate burst read cycle via reset xxxxhigh-zlxx terminate current burst read cycle and start new burst read cycle l h h add in add in h product introduction the k8s6415e is an 64mbit (67,108,364 bits) nor-type burst flash memory. the device fe atures 1.8v single voltage power supply operating within the range of 1.7v to 1.95v. the device is progr ammed by using the channel hot electron (che) injection mecha- nism which is used to program eproms. t he device is erased elec trically by using fo wler-nordheim tunneling mechanism. to pro- vide highly flexible erase and program capabi lity, the device adapts a block memory architecture that divides its memory array into 135 blocks (32-kword x 127 , 4-kword x 8, ). programming is done in units of 16 bits (word). all bits of data in one or multipl e blocks can be erased when the device executes the erase operation. to pr event the device from accidental erasing or over-writing the p ro- grammed data, 135 memory blocks can be hardware protected. r egarding read access time, at 54 mhz, the k8s6415e provides a burst access of 14.5ns with initial access times of 90ns at 30pf. at 66mhz, the k8s6415e provides a burst access of 11ns with i nitial access times of 70ns at 30pf. the command set of k8s6415e is compatible with standard flash devices. the device uses chip enable (ce ), write enable (we ), address valid(avd ) and output enable (oe ) to control asynchronous read and write operation. for burst operations, the device additi onally requires ready (rdy) and clock (clk). de vice operations are exec uted by selective com - mand codes. the command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing. the command codes serve as inputs to an internal state machine which controls the program/erase c ir- cuitry. register contents also internally latch addresses and dat a necessary to execute the program and erase operations. the k8s6415e is implemented with internal program/erase routines to execute the program/erase operations. the internal program/ erase routines are invoked by program/erase command sequences. the internal program routine automatically programs and ver- ifies data at specified address. the internal erase routine auto matically pre-programs the memory cell which is not programmed and then executes the erase operation. the k8s 6415e has means to indicate the status of completion of program/erase operations. the status can be indicated via data polling of dq7, or the toggle bit (dq6). once the operations have been completed, the device a uto- matically resets itself to the read mode. the device requires only 25 ma as burst and asynchronous mode read current and 15 ma for program/erase operations.
flash memory k8s6415et(b)b revision 1.1 january, 2006 9 table 5. command sequences command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle asynchronous read add 1 ra data rd reset(note 5) add 1 xxxh data f0h autoselect manufacturer id(note 6) add 4 555h 2aah (da)555h (da)x00h data aah 55h 90h ech autoselect device id(note 6) add 4 555h 2aah (da)555h (da)x01h data aah 55h 90h note6 autoselect block protection verify(note 7) add 4 555h 2aah (ba)555h (ba)x02h data aah 55h 90h 00h / 01h program add 4 555h 2aah 555h pa data aah 55h a0h pd unlock bypass add 3 555h 2aah 555h data aah 55h 20h unlock bypass program(note 8) add 2 xxx pa data a0h pd unlock bypass block erase(note 8) add 2 xxx ba data 80h 30h unlock bypass chip erase(note 8) add 2 xxxh xxxh data 80h 10h unlock bypass reset add 2 xxxh xxxh data 90h 00h quadruple word accelerated program(note9) add 5 xxx pa1 pa2 pa3 pa4 data a5h pd1 pd2 pd3 pd4 chip erase add 6 555h 2aah 555h 555h 2aah 555h data aah 55h 80h aah 55h 10h block erase add 6 555h 2aah 555h 555h 2aah ba data aah 55h 80h aah 55h 30h erase suspend (note 10) add 1 (da)xxxh data b0h erase resume (note 11) add 1 (da)xxxh data 30h program suspend (note12) add 1 (da)xxxh data b0h program resume (note11) add 1 (da)xxxh data 30h command definitions the k8s6415e operates by selecting and executing its operational modes. each operational mode has its own command set. in order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg- ister. writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. the defined valid register command sequences are stated in table 5.
flash memory k8s6415et(b)b revision 1.1 january, 2006 10 table 5. command sequences (continued) command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle block protection/unprotection (note 13) add 3 xxx xxx abp data 60h 60h 60h cfi query (note 14) add 1 (da)x55h data 98h set burst mode configuration register (note 15) add 3 555h 2aah (cr)555h data aah 55h c0h enter otp block region addr 3 555h 2aah 555h data aah 55h 70h exit otp block region addr 4 555h 2aah 555h xxx data aah 55h 75h 00h notes: 1. ra : read address , pa : program address, rd : read data, pd : program data , ba : block address (a21 ~ a12) da : bank address (a21 ~ a18) , abp : address of the bloc k to be protected or unprotected , cr : configuration register set ting 2. the 4th cycle data of autoselect mode and rd are output data. the others are input data. 3. data bits dq15?dq8 are don?t care in command sequences, except for rd, pd and device id. 4. unless otherwise noted, address bits a21 ~ a11 are don?t cares. 5. the reset command is required to return to read mode. if a bank entered the autoselect mode during the erase su spend mode, writing the reset command returns that bank to the era se suspend mode. if a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the p rogram suspend mode. if dq5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase s uspend mode if that bank was in erase suspend mode. 6. the 3rd and 4th cycle bank address of autoselect mode must be same. device id data : "2250h" for top boot block device, "2251h" for bottom boot block device 7. normal block protection verify : 00h for an unprotected block and 01h for a protected block. otp block protect verify (with otp block address afte r entering otp block) : 00h for unlocked, and 01h for locked. 8. the unlock bypass command sequence is required prior to this command sequence. 9. quadruple word accelerated program is invoked only at vpp=v id ,vpp setup is required prior to this command sequence. pa1, pa2, pa3, pa4 have the same a21~a2 address. 10. the system may read and program in non-erasing blocks when in the erase suspend mode. the system may enter the autoselect mode when in the erase suspend mode. the erase suspend command is valid only during a block erase operation, and requires the bank address. 11. the erase/program resume command is valid only during t he erase/program suspend mode, and requires the bank address. 12. this mode is used only to enable data read by suspending the program operation. 13. set block address(ba) as either a6 = v ih , a1 = v ih and a0 = v il for unprotected or a6 = v il , a1 = v ih and a0 = v il for protected. 14. command is valid when the device is in read mode or autoselect mode. 15. see "set burst mode congiguration register" for details.
flash memory k8s6415et(b)b revision 1.1 january, 2006 11 device operation the device has i/os that accept both addr ess and data information. to write a comm and or command sequence (which includes pro- gramming data to the device and erasing blocks of memory), the system must drive clk, avd and ce to v il and oe to v ih when providing an address to the device, and drive clk, we and ce to v il and oe to v ih when writing commands or data. the device provide the unlock bypass mode to save its program time for program operation. unlike the standard program command sequence which is comprised of four bus cycles, only two program cycles are requir ed to program a word in the unlock bypass mode. one block, multiple blocks, or the entire device can be erased. table 3 indica tes the address space that each block occup ies. the device?s address space is divided into sixteen banks: bank 0 contains the boot/par ameter blocks, and the other banks(from b ank 1 to 15) consist of uniform blocks. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?bloc k address? is the address bits required to uniquely select a block. i cc2 in the dc characteristics table repr esents the active current specification for the write mode. the ac characteristics section contains ti ming specification tables and timi ng diagrams for write operation s. read mode the device automatically enters to asynchronous read mode after device power-up. no commands are required to retrieve data in asynchronous mode. after completing an internal program/erase r outine, each bank is ready to read array data. the reset com- mand is required to return a bank to the read(or erase-suspend-r ead)mode if dq5 goes high during an active program/erase opera- tion, or if the bank is in the autoselect mode. the synchronous(burst) mode will automatically be enabled on the first rising edge on the clk input while avd is held low. that means device enters burst read mode from asynchr onous read mode to burst read mode using clk and avd signal. when the burst read is finished(or terminated), the device retu rn to asynchronous read mode automatically. asynchronous read mode for the asynchronous read mode a valid address should be assert ed on a/dq0-a/dq15 and a16-a21, while driving avd and ce to v il . we should remain at v ih . note that clk must remain low for asynchronous read mode. the address is latched at the rising edge of avd , and then the system can drive oe to v il . the data will appear on a/dq0-a/dq15. since the memory array is divided into sixteen banks, each bank remains enabled for read access until the command register contents are altered. address access time (t aa ) is equal to the delay from valid addresses to va lid output data. the chip enable access time(t ce ) is the delay from the falling edge of ce to valid data at the outputs . the output enable access time(t oe ) is the delay from the falling edge of oe to valid data at the output. the asynchronous access time is measured from a valid address, falling edge of avd or falling edge of ce whichever occurs last. to prevent the memory content from s purious altering during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset. synchronous (burst) read mode the device is capable of conti nuous linear burst operation and linear burst operation of a preset length. for the burst mode, t he sys- tem should determine how many clock cyc les are desired for the initial word(t iaa ) of each burst access and what mode of burst oper- ation is desired using "burst mode confi guration register" command sequences. see "set burst mode configuration" for further details. the status data also can be re ad during burst read mode by using avd signal with a bank address. to initiate the synchro- nous read again, a new address and avd pulse is needed after the host has completed status reads or the device has completed the program or erase operation. continuous linear burst read the synchronous(burst) mode will automatically be enabled on the first rising edge on the clk input while avd is held low. note that the device is enabled for asynchronous mode when it first powers up. the initial word is output t iaa after the rising edge of the first clk cycle. subsequent words are output t ba after the rising edge of each successive cl ock cycle, which automatically increments the internal address counter. note that the device has internal addres s boundary that occurs every 16 words. when the device is cro ss- ing the first word boundary, additional cl ock cycles are needed before data appears for the next address. the number of addtion al clock cycle can vary from zero to three cycles, and the ex act number of additional clock cy cle depends on the starting address of burst read.(refer to figure 13) the rdy output indicates this condition to the system by pulsi ng low. the device will continue to out- put sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until th e system asserts ce high, reset low or avd low in conjunction with a new address.(see table 4.) the reset command does not ter- minate the burst read operation. if the host system crosses the bank boundary while reading in burst mode, and the accessed bank is not programming or erasing, a additional clock cycles are needed as previously mentioned. if the host system crosses the bank boundary while the accessed ban k is programming or erasing, that is busy bank , the synchronous read will be terminated.
flash memory k8s6415et(b)b revision 1.1 january, 2006 12 8-,16-word linear burst read as well as the continuous linear burst mode, there are two(8 & 16 word) linear wrap & no-wrap mode, in which a fixed number of words are read from consecutive addresses. in these modes, the addresses for burst r ead are determined by the group within whi ch the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode.(see table. 6) as an example: in wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap b urst sequence would be 2-3-4-5-6-7-0-1h. the burst sequence begins with t he starting address written to the device, but wraps back t o the first address in the selected group. in a similar manner, 16-word wrap mode begin their burst sequence on the starting addr ess written to the device, and then wrap back to the first address in the selected address group. in no-wrap mode case, if the starting address in the 8-word mode is 2h, the no-wrap burst sequenc e would be 2-3-4-5-6-7-8-9h. t he burst sequence begins with the starting address written to the de vice, and continue to the 8th address from starting address. i n a sim- ilar manner, 16-word no-wrap mode begin their burst sequence on the starting address written to the device, and continue to the 16th address from starting address. also, when the address cross the word boundary in no-wr ap mode, same number of additional clock cycles as continuous linear mode is needed. programmable wait state the programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after avd is driven active for burst read mode. upon power up, the number of total initial access cycles defaults to seven. handshaking the handshaking feature allows the host system to simply monitor the rdy signal from the device to determine when the initial w ord of burst data is ready to be read. to set the number of initia l cycle for optimal burst mode, the host should use the programma ble wait state configuration.(see "set burst mode configurati on register" for details.) the rising edge of rdy after oe goes low indicates the initial word of valid burst data. using the autoselect co mmand sequence the handshaking feature may be verified in the devi ce. set burst mode configuration register the device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. the burst mode configuration register mu st be set before the device enter burst mode. the burst mode configuration register is loaded with a three- cycle command sequences. on the third cycle, the data should be c0 h, address bits a11-a0 should be 555h, and address bits a18-a12 set the code to be latched. the device will power up or after a ha rd- ware reset with the default setting. table 6. burst address groups(wrap mode only) burst mode group size group address ranges 8 word 8 words 0-7h, 8-fh, 10-17h, .... 16 word 16 words 0-fh, 10-1fh, 20-2fh, .... table 7. burst mode configuration register table address bit function settings(binary) a18 rdy active 1 = rdy active one clock cycle before data 0 = rdy active with data(default) a17 burst read mode 000 = continuous(default) 001 = 8-word linear with wrap 010 = 16-word linear with wrap 011 = 8-word linear with no-wrap 100 = 16-word linear with no-wrap 101 ~ 111 = reserve a16 a15 a14 programmable wait state 000 = data is valid on the 4th active clk edge after avd transition to v ih 001 = data is valid on the 5th active clk edge after avd transition to v ih 010 = data is valid on the 6th active clk edge after avd transition to v ih 011 = data is valid on the 7th active clk edge after avd transition to v ih (default) 100 = reserve 101 = reserve 110 = reserve 111 = reserve a13 a12 programmable wait state configuration this feature informs the device of the numbe r of clock cycles that must elapse afte r avd# is driven active before data will be avail- able. this value is determined by the in put frequency of the device. address bits a 14-a12 determine the setting. (see burst mod e configuration register table)
flash memory k8s6415et(b)b revision 1.1 january, 2006 13 the programmable wait state setting instructs the device to set a particular number of clock cycles for the initial access in b urst mode. note that hardware reset will set the wait state to the default setting, that is 7 initial cycles. burst read mode setting the device supports five different burst r ead modes : continuous linear mode, 8 and 16 word linear burst modes with wrap and 8 and 16 word linear burst modes with no-wrap. rdy configuration by default, the rdy pin will be hi gh whenever there is valid data on the output. the device can be set so that rdy goes active one data cycle before active data. address bit a18 determine this setting. note that rdy always go high with valid data in case of word boundary crossing. autoselect mode by writing the autoselect command sequences to the system, the device enters the autoselect mode. this mode can be read only by asynchronous read mode. the system can then read autoselect codes from the internal register(which is separate from the memory array). standard asynchronous read cycle timings apply in this mode. the device offers the autoselect mode to identify manufact urer and device type by reading a binary code. in addi tion, this mode allows the host system to verify the block protection or unpro tection. table 5 shows the address and data requirements. the autoselec t command sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or progr am-suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing in the device. the autoselect co mmand sequence is initiated by first writin g two unlock cycles. this is fo llowed by a third write cycle that contains the addr ess and the autoselect command. note that the bloc k address is needed for the verification of block protection. the system may read at any address within the same bank any number of times without initiating another autoselect command sequence. and the burst read should be prohibited during autoselect mode. t o terminate the autoselect operation, write reset command(f0h) into the command register. standby mode when the ce and reset inputs are both held at v cc 0.2v or the system is not reading or writing, the device enters stand-by mode to minimize the power consumption. in this mode, the devic e outputs are placed in the high impedence state, independent of the oe input. when the device is in either of these standby modes, the device requires standard access time (tce ) for read access bef ore it is ready to read data. if the device is des elected during erasure or programming, the device draws active current until the ope ration is completed. i cc5 in the dc characteristics table repres ents the standby current specification. automatic sleep mode the device features automatic sleep mode to minimize the device power consumption during both asynchronous and burst mode. when addresses remain stable for t aa +60ns, the device automatically enables this mode. the automatic sleep mode is independent of the ce , we , and oe control signals. in a sleep mode, output data is latc hed and always available to the system. when addresses are changed, the device provides new data without wait time. automatic sleep mode current is equal to standby mode current. table 8. burst address sequences start addr. burst address sequence(decimal) continuous burst 8-word burst 16-word burst wrap 0 0-1-2-3-4-5-6... 0-1-2-3-4-5-6-7 0-1-2-3 ... -d-e-f 1 1-2-3-4-5-6-7... 1-2-3-4-5-6-7-0 1-2-3-4 ... -e-f-0 2 2-3-4-5-6-7-8... 2-3-4-5-6-7-0-1 2-3-4-5 ... -f-0-1 . . . . . . . . no-wrap 0 0-1-2-3-4-5-6... 0-1-2-3-4-5-6-7 0-1-2-3 ... -d-e-f 1 1-2-3-4-5-6-7... 1-2-3-4-5-6-7-8 1-2-3-4 ... -e-f-10 2 2-3-4-5-6-7-8... 2-3-4-5-6-7-8-9 2-3-4-5 ... -f-0-11 . . . . . . . . table 9. autoselect mode description description address read data manufacturer id (da) + 00h ech device id (da) + 01h 2250h(top boot block), 2251h(bottom boot block) block protection/unprotection (ba) + 02h 01h (protected), 00h (unprotected)
flash memory k8s6415et(b)b revision 1.1 january, 2006 14 output disable mode when the oe input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. block protection & unprotection to protect the block from accidental writ es, the block protection/unprotection command s equence is used. on power up, all block s in the device are protected. to unprotect a block, the system must write the block protection/unprotection command sequence. the f irst two cycles are written: addresses are don?t care and data is 60h. using the third cycle, the block address (abp) and command (6 0h) is written, while specifying with addresses a6, a1 a nd a0 whether that block should be protected (a6 = v il, a1 = v ih , a0 = v il ) or unprotected (a6 = v ih, a1 = v ih , a0 = v il ). after the third cycle, the system can conti nue to protect or unprotect additional cycles, or exit the sequence by writing f0h (reset command). the device offers three types of data protection at the block level: ? the block protection/unprotection command sequence disables or re-enables both program and erase operations in any block. ? when wp is at v il , the two outermost blocks are protected. ? when v pp is at v il , all blocks are protected. note that user never float the v pp and wp , that is, vpp is always connected with v ih , v il or v id and wp is v ih or v il . hardware reset the device features a hardware method of resetting the device by the reset input. when the reset pin is held low(v il ) for at least a period of trp, the device immediately te rminates any operation in progress, tris tates all outputs, and ignores all read/write com- mands for the duration of the reset pulse. the device also resets the internal state machine to asynchronous read mode. to ensure data integrity, the interrupted operation should be reinit iated once the device is ready to accept another command seque nce. as previously noted, when reset is held at v ss 0.2v, the device enters standby mode. the reset pin may be tied to the system reset pin. if a system reset occurs during the internal program or erase routine, the device will be automatically reset to the asyn- chronous read mode; this will enable the systems microprocessor to read the boot-up firmware from the flash memory. if reset is asserted during a program or erase operation, the device require s a time of tready (during internal routines) before the device is ready to read data again. if reset is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tready (not during internal routines). trh is needed to read data after reset returns to v ih . refer to the ac char- acteristics tables for reset parameters and to figure 6 for the timing diagram. software reset the reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. the addresses are in don?t care state. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins, or in an program command seq uence before programming begins. if the device begins erasure or programming, the reset command is ignored until the operation is completed. if the program command sequence is written to a ban k that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. the reset com- mand valid between the sequence cycles in an autoselect command s equence. in an autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset co m- mand returns that bank to the erase-suspend-read mode. also, if a bank entered the autoselect mode while in the program suspend mode, writing the reset command returns that bank to the progr am-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the re ad mode. (or erase-suspend-read mode if the bank was in erase suspend) program the k8s6415e can be programmed in units of a word. programming is writing 0's into the memory array by executing the internal program routine. in order to perform the internal program ro utine, a four-cycle command seque nce is necessary. the first two cycles are unlock cycles. the th ird cycle is assigned for the program setup command. in the last cycle, the address of the memo ry location and the data to be programmed at that location are wr itten. the device automaticall y generates adequate program pulses and verifies the programmed cell margin by the internal program routine. during the execution of the routine, the system is not required to provide further controls or ti mings. during the internal program routine, commands written to the device will be ig nored. note that a hardware reset during a program operation will cause data corruption at the corresponding location. accelerated program operation the device provides single/quadruple word ac celerated program operations through the vpp input. using this mode, faster manu- facturing throughput at the factory is possible. when v id is asserted on the vpp input, the device automatically enters the unlock bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. by removing v id returns the device to normal operation mode. note that read while accelerated program and program suspend mode are not guaranteed
flash memory k8s6415et(b)b revision 1.1 january, 2006 15 single word accelerated program operation the system would use two-cycle program sequence (one-cycle ( xxx - a0h) is for single word program command, and next one- cycle (pa - pd) is for program address and data ). quadruple word accelerated program operation as well as single word accelerated program, the system would use five-cycle program sequence (o ne-cycle (xxx - a5h) is for qua - druple word program command, and four cycles are for program address and data). ? only four words programming is possible ? each program address must have the same a21~a2 address ? the device automatically generates adequate program pu lses and ignores other command after program command ? program/erase cycling must be limited below 100cycles for optimum performance. ? read while write mode is not guaranteed requirements : ambient temperature : t a =30 c 10 c unlock bypass the k8s6415e provides the unlock bypass mode to save its operat ion time. this mode is possible for program, block erase and chi p erase operation. there are two methods to enter the unlock bypass mode. the mode is invoked by the unlock bypass command sequence or the assertion of v id on v pp pin. unlike the standard program/erase comm and sequence that contains four bus cycles, the unlock bypass program/erase command sequence comprises onl y two bus cycles. the unlock bypass mode is engaged by issu- ing the unlock bypass command sequenc e which is comprised of three bus cycles. writing first two unl ock cycles is followed by a third cycle containing the unlock bypass command (20h). once the device is in the unlock bypass mode, the unlock bypass pro- gram/erase command sequence is necessary. the unlock bypass pr ogram command sequence is compri sed of only two bus cycles; writing the unlock bypass program command (a0h) is followed by the program address and data. this command sequence is the only valid one for programming the device in the unlock bypass m ode. also, the unlock bypass erase command sequence is com- prised of two bus cycles; writing the unloc k bypass block erase command(80h-30h) or wr iting the unlock bypass chip erase com- mand(80h-10h). this command sequences are the only valid ones fo r erasing the device in the unl ock bypass mode. the unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. the unlock bypass reset command sequence consists of two bus cycles. the first cycle must contain the data (90h ). the second cycle contains only the da ta (00h). then, the device returns to the read mode. to enter the unlock bypass mode in hardware level, the v id also can be used. by assertion v id on the v pp pin, the device enters the unlock bypass mode. also, the all blocks are te mporarily unprotected when the device using the v id for unlock bypass mode. to exit the unlock bypass mode, just remove the asserted v id from the v pp pin.(note that user never float the v pp , that is, vpp is always connected with v ih , v il or v id . ) . chip erase to erase a chip is to write 1 s into the entire memory array by executing the inte rnal erase routine. the chip erase requires six bus cycles to write the command sequence. the erase set-up command is written after first two "unlock" cycles. then, there are two more write cycles prior to writing the chip erase command. the internal erase routine automatic ally pre-programs and verifies t he entire memory for an all zero data pattern prior to erasi ng. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when dq7 is "1". after that the device returns to the read mode. block erase to erase a block is to write 1 s into the desired memory block by executing the in ternal erase routine. the block erase requires six bus cycles to write the command sequence shown in table 5. after the first two "unlock" cycles, the erase setup command (80h) i s written at the third cycle. then there are tw o more "unlock" cycles followed by the bl ock erase command. the internal erase rou tine automatically pre-programs and verifies the entire memory prio r to erasing it. the block addr ess is latched on the rising edge of avd , while the block erase command is latched on the rising edge of we . multiple blocks can be erased sequentially by writing the sixth bus-cycle. upon completion of the last cy cle for the block erase, additional block address and the block erase command (30h) ca n be written to perform the multi-block erase. for the multi-bl ock erase, only sixth cycle(bloc k address and 30h) is needed.(simi larly, only second cycle is needed in unlock bypass block erase.) an 50us (typical) "time window" is required between the block erase command writes. the block erase command must be written with in the 50us "time window", otherwise the block erase command will be ignored. the 50us "time window" is reset when the falling edge of the we occurs within the 50us of "time window" to latch the block erase command. during the 50us of "time window", any co mmand other than the block erase or the erase suspend command written to the device will reset the device to read mode. after the 50 us of "time window", the block erase command will initia te the internal erase routine to erase the selected blocks. any block erase address and command follo wing the exceeded "time window" may or may not be accepted. no other commands will be rec ognized except the erase suspend command during block erase oper- ation. the device provides accelerated erase o perations through the vpp input. when v id is asserted on the vpp input, the device auto- matically enters the unlock bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for erase. by removing v id returns the device to normal operation mode.
flash memory k8s6415et(b)b revision 1.1 january, 2006 16 erase suspend / resume the erase suspend command interrupts the block erase to read or pr ogram data in a block that is not being erased. also, it is p os- sible to protect or unprotect of the block that is not being erased in erase suspend mode. the erase suspend command is only va lid during the block erase operation including the time window of 50 us . the erase suspend command is not valid while the chip eras e or the internal program routine sequence is running. when the erase suspend command is written during a block erase operation, the device requires a maximum of 20 us(recovery time) to suspend the erase operation. therefore system must wait for 20us(rec ov- ery time) to read the data from the bank which include the bloc k being erased. otherwise, system can read the data immediately from a bank which don?t include the block being erased without recovery time(max. 20us) after erase su spend command. and, after the maximum 20us recovery time, the device is availble for programmi ng data in a block that is not being erased. but, when the eras e suspend command is written during the block erase time window ( 50 us) , the device immediately te rminates the block erase time window and suspends the erase operation. the system may also wr ite the autoselect command sequence when the device is in the erase suspend mode. when the erase resume command is executed, the block erase op eration will resume. when the erase sus- pend or erase resume command is executed, the addresses are in don't care state. program suspend / resume the device provides the program suspend/resume mode. this mode is used to enable data read by suspending the program operation. the device accepts a program suspend command in program mode(including program operations performed during erase suspend) but other commands are ignored. after input of the program suspend command, 2us is needed to enter the pro- gram suspend read mode. therefore system must wait for 2us(recovery time) to read the data from the bank which include the block being programmed. othwewis e, system can read the data immediately from a bank which don't include block being pro- grammed without ecovery time(max. 2us) after program sus pen command. like an erase suspend mode, the device can be returned to program mode by using a program resume command. read while write operation the device is capable of reading data from one bank while writi ng in the other banks. this is so called the read while write o pera- tion. an erase operation may also be suspended to read from or program to another location within the same bank(except the bloc k being erased). the read while write operation is prohibited during the chip erase operation. figure 12 shows how read and write cycles may be initiated for simultaneous operation with zero lat ency. refer to the dc characteristics table for read-while-writ e current specifications. otp block region the otp block feature provides a 256-byte flash memory regi on that enables permanent part identification through an electronic serial number (esn). the otp bl ock is customer lockable and shipped with itself unlocked, allowing customers to untilize the th at block in any manner they choose. the custom er-lockable otp block has the protection ve rify bit (dq0) set to a "0" for unlocked state or a "1" for locked state. the system accesses the otp block through a command sequenc e (see "enter otp block / exit otp block command sequence" at table8). after the system has written the "enter otp blo ck" command sequence, it may read the otp block by using the addresses (7fff80h~7fffffh) normally and may check the protection verify bit (dq0) by using th e "autoselect block protection verify" command sequence with otp block address. this mode of ope ration continues until the system issues the "exit otp block" command suquence, a hardware reset or until power is removed fr om the device. on power-up, or following a hardware reset, the device reverts to sending commands to main blocks. note that the accelerated function and unlock bypass modes are not available when the otp block is enabled. customer lockable in a customer lockable device, the otp block is one-time pr ogrammable and can be locked only once. note that the accelerated programming and unlock bypass functions are not available when pr ogramming the otp block. locking operation to the otp block is started by writing the "enter otp bl ock" command sequence, and then the "block protection" command sqeunce (table 8) with an otp block address. hardware reset terminates locking operati on, and then makes exiting from otp block. the locking opera- tion has to be above 100us. the otp block lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the bits in the otp block space can be modified in any way. write pulse ?glitch? protection noise pulses of less than 5ns (typical) on oe , ce, avd or we do not initiate a write cycle.
flash memory k8s6415et(b)b revision 1.1 january, 2006 17 dq7 : data polling when an attempt to read the device is made while executing the inte rnal program, the complement of the data is written to dq7 a s an indication of the routine in progress. when the routine is comp leted an attempt to access to the device will produce the tru e data written to dq7. when a user attempts to read the block being er ased, dq7 will be low. if the device is placed in the erase/prog ram suspend mode, the status can be detected via the dq7 pin. if the system tries to read an address which belongs to a block that is being erase suspended, dq7 will be high. and, if the system tr ies to read an address which belongs to a block that is being pro gram suspended, the output will be the true data of dq7 itself. if a non-erase-suspended or non-program-suspended block address is read, the device will produce the true data to dq7. if an attempt is made to program a protected block, dq7 outputs complements the data for approximately 1 s and the device then returns to the read mode without changing data in the block. if an attempt is made to erase a protected block, dq7 outputs complement dat a in approximately 100us and the device then returns to the read mode without erasing the data in the block. low v cc write inhibit to avoid initiation of a write cycle during vcc power-up and power-down, a write cycle is locked out for vcc less than v lko . if the vcc < v lko (lock-out voltage), the command register and all internal program/erase circuits are disa bled. under this condition the device will reset itself to the read mode.subsequent writes will be ignored until the vcc level is greater than v lko . it is the user?s responsibility to ensure that the control pins are logicall y correct to prevent unintentiona l writes when vcc is above v lko. logical inhibit write cycles are inhibit ed by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle, ce and we must be a log- ical zero while oe is a logical one. power-up protection to avoid initiation of a write cycle during v cc power-up, reset low must be asserted during power-up. after reset goes high. the device is reset to the read mode. flash memory status flags the k8s6415e has means to indicate its status of operation in the bank where a program or erase operation is in processes. address must include bank address being executed internal routine operation. the status is indicated by raising the device stat us flag via corresponding dq pins. the status data c an be read during burst read mode by using avd signal with a bank address. that means status read is supported in synchrono us mode. if status read is performed, the data provided in the burst read is identic al to the data in the initial access. to initiate the synchronous read again, a new address and avd pulse is needed after the host has completed status reads or the device has completed the progra m or erase operation. the corr esponding dq pins are dq7, dq6, dq5, dq3 and dq2. table 10. hardware sequence flags notes : 1. dq2 will toggle when the device performs successive read operations from the erase/program suspended block. 2. if dq5 is high (exceeded timing limits), successive reads from a problem block will cause dq2 to toggle. status dq7 dq6 dq5 dq3 dq2 in progress programming dq7 toggle 0 0 1 block erase or chip erase 0 toggle 0 1 toggle erase suspend read erase suspended block 1100 toggle (note 1) erase suspend read non-erase suspended block data data data data data erase suspend program non-erase suspended block dq7 toggle 0 0 1 program suspend read program suspended block dq7 1 0 0 toggle (note 1) program suspend read non- program suspended block data data data data data exceeded time limits programming dq7 toggle 1 0 no toggle block erase or chip erase 0 toggle 1 1 (note 2) erase suspend program dq7 toggle 1 0 no toggle
flash memory k8s6415et(b)b revision 1.1 january, 2006 18 dq6 : toggle bit toggle bit is another option to detect whether an internal routine is in progress or completed. once the device is at a busy st ate, dq6 will toggle. toggling dq6 will stop afte r the device completes its internal routi ne. if the device is in the erase/program suspend mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of dq 6. if an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at dq6. if an attempt is made to program a protected block, dq6 toggles fo r approximately 1us and the device then returns to the read mode without changing the data in the block. if an attempt is made to erase a protected block, dq6 toggles for approximately 100 s and the device then returns to the read mode without erasing the data in the block. dq5 : exceed timing limits if the internal program/erase routine extends beyond the timi ng limits, dq5 will go high, indi cating program/erase failure. dq3 : block erase timer the status of the multi-block erase operation can be detected via the dq3 pin. dq3 will go high if 50 s of the block erase time win- dow expires. in this case, the internal erase routine will init iate the erase operation.therefore, the device will not accept f urther write commands until the erase operation is complete d. dq3 is low if the block erase time wi ndow is not expired. within the block era se time window, an additional block erase comm and (30h) can be accepted. to confirm that the block erase command has been accepted, the software may check the status of dq3 following each block erase command. dq2 : toggle bit 2 the device generates a toggling pulse in dq 2 only if an internal erase routine or an erase/program suspend is in progress. when the device executes the internal erase rout ine, dq2 toggles only if an erasing block is read. although the internal erase routi ne is in the exceeded time limits, dq2 toggles on ly if an erasing block in the exceeded time limits is read. when the device is in th e erase/program suspend mode, dq2 toggles only if an address in t he erasing or programming block is read. if a non-erasing or non - programmed block address is read during the erase/program suspend mode, then dq2 will produce valid data. dq2 will go high if the user tries to program a non-erase suspend blo ck while the device is in the erase suspend mode. rdy: ready normally the rdy signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. if rdy is low state, data is not valid at expected time, and if high state, data is valid. note that, if ce is low and oe is high, the rdy is high state. start dq7 = data ? no dq5 = 1 ? fail pass yes figure 1. data polling algorithms figure 2. toggle bit algorithms dq7 = data ? no no yes read(dq0~dq7) valid address read(dq0~dq7) valid address start dq6 = toggle ? no dq5 = 1 ? fail pass no dq6 = toggle ? yes yes no read twice(dq0~dq7) valid address read(dq0~dq7) valid address yes yes read(dq0~dq7) valid address
flash memory k8s6415et(b)b revision 1.1 january, 2006 19 commom flash memory interface common flash momory interface is contrived to increase the compatibility of host syst em software. it provides the specific inf orma- tion of the device, such as memory size and electrical features. once this informat ion has been obtained, the system software w ill know which command sets to use to enable flash wr ites, block erases, and control the flash component. when the system writes the cfi command(98h) to address 55h , the device enters the cfi mode. and then if the system writes the address shown in table 11, the system can read the cfi data. q uery data are always presented on the lowest-order data out- puts(dq0-7) only. in word(x16) mode, the upper data outputs(dq8-15) is 00h. to terminate this operation, the system must write the reset command. table 11. common flash memory interface code description addresses (word mode) data query unique ascii string "qry" 10h 11h 12h 0051h 0052h 0059h primary oem command set 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = none exists) 17h 18h 0000h 0000h address for alternate oem ex tended table (00h = none exists) 19h 1ah 0000h 0000h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1bh 0017h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 0019h vpp(acceleration program) supply minimum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 1dh 0085h vpp(acceleration program) supply maximum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 1eh 0095h typical timeout per single word write 2 n us 1fh 0004h typical timeout for min. size buffer write 2 n us(00h = not supported) 20h 0000h typical timeout per individual block erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms(00h = not supported) 22h 0011h max. timeout for word write 2 n times typical 23h 0005h max. timeout for buffer write 2 n times typical 24h 0000h max. timeout per individual block erase 2 n times typical 25h 0004h max. timeout for full chip erase 2 n times typical(00h = not supported) 26h 0000h device size = 2 n byte 27h 0017h flash device interface description 28h 29h 0000h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block r egions within device 2ch 0002h
flash memory k8s6415et(b)b revision 1.1 january, 2006 20 table 11. common flash memory interface code (continued) description addresses (word mode) data erase block region 1 information bits 0~15: y+1=block number bits 16~31: block size= z x 256bytes 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 2 information 31h 32h 33h 34h 007eh 0000h 0000h 0001h erase block region 3 information 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 4 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h query-unique ascii string "pri" 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0032h minor version number, ascii 44h 0030h address sensitive unlock(bits 1-0) 0 = required, 1= not required silcon revision number(bits 7-2) 45h 0000h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 46h 0002h block protect 00 = not supported, 01 = supported 47h 0001h block temporary unprotect 00 = not supported, 01 = supported 48h 0000h block protect/unprotect scheme 00 = not supported, 01 = supported 49h 0001h simultaneous operation 00 = not supported, 01 = supported 4ah 0001h burst mode type 00 = not supported, 01 = supported 4bh 0001h page mode type 00 = not supported, 01 = 4 word page 02 = 8 word page 4ch 0000h max. operating clock frequency (mhz ) 4eh 0042h rww(read while write) functionality restrictio n (00h = non exists , 01h = exists) 4fh 0000h handshaking 00 = not supported at both mode, 01 = supported at sync. mode 10 = supported at async. mode, 11 = supported at both mode 50h 0001h
flash memory k8s6415et(b)b revision 1.1 january, 2006 21 absolute maximum ratings notes : 1. minimum dc voltage is -0.5v on input/ output pins. during transitions, this level may fall to -2.0v for periods <20ns. maximum dc voltage is vcc+0.6v on input / output pins wh ich, during transitions, may overs hoot to vcc+2.0v for periods <20n s. 2. minimum dc input voltage is -0.5v on v pp . during transitions, this level may fall to -2.0v for periods <20ns. maximum dc input voltage is +9.5v on v pp which, during transitions, may ov ershoot to +12.0v for periods <20ns. 3. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. ex posure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss vcc vcc -0.5 to +2.5 v v pp v in -0.5 to +9.5 all other pins -0.5 to +2.5 temperature under bias commercial t bias -10 to +125 c extended -25 to +125 storage temperature t stg -65 to +150 c short circuit output current i os 5ma operating temperature t a (commercial temp.) 0 to +70 c t a (extended temp.) -25 to + 85 c dc characteristics parameter symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc , v cc =v ccmax - 1.0 - + 1.0 a vpp leakage current i lip v cc =v ccmax , v pp =9.5v - - 35 a output leakage current i lo v out =v ss to v cc , v cc =v ccmax , oe =v ih - 1.0 - + 1.0 a active burst read current i ccb1 ce =v il , oe =v ih (continuous burst, 66mhz) - 24 36 ma active asynchronous read current i cc1 ce =v il , oe =v ih 10mhz - 27 40 ma 1mhz - 3 5 ma active write current (note 2) i cc2 ce =v il , oe =v ih , we =v il , v pp =v ih -1530ma read while write current i cc3 ce =v il , oe =v ih -4070ma accelerated program current i cc4 ce =v il , oe =v ih , v pp =9.5v - 15 30 ma standby current i cc5 ce = reset =v cc 0.2v - 15 50 a standby current during reset i cc6 reset = v ss 0.2v - 15 50 a automatic sleep mode(note 3) i cc7 ce =v ss 0.2v, other pins=v il or v ih v il = v ss 0.2v, v ih = v cc 0.2v -1550 a input low voltage v il -0.5 - 0.4 v input high voltage v ih v cc -0.4 - v cc +0.4 v output low voltage v ol i ol = 100 a , v cc =v ccmin - - 0.1 v output high voltage v oh i oh = -100 a , v cc =v ccmin v cc -0.1 - - v voltage for accelerated program v id 8.5 9.0 9.5 v low v cc lock-out voltage v lko 1.0 - 1.3 v recommended operating conditions ( voltage reference to gnd ) parameter symbol min typ. max unit supply voltage v cc 1.7 1.8 1.95 v supply voltage v ss 000v notes: 1. maximum i cc specifications are tested with v cc = v cc max. 2. i cc active while internal erase or internal program is in progress. 3. device enters automatic sleep mode when addresses are stable for t aa + 60ns.
flash memory k8s6415et(b)b revision 1.1 january, 2006 22 ac test condition parameter value input pulse levels 0v to v cc input rise and fall times 5ns input and output timing levels v cc /2 output load c l = 30pf 0v v cc v cc /2 v cc /2 input pulse and test point input & output test point capacitance (t a = 25 c, v cc = 1.8v, f = 1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 10 pf output capacitance c out v out =0v - 10 pf control pin capacitance c in2 v in =0v -10pf ac characteristics output load device under te s t * c l = 30pf including scope and jig capacitance synchronous/burst read parameter symbol 7b (54 mhz) 7c (66 mhz) unit min max min max initial access time t iaa - 88.5 - 70 ns burst access time valid clock to output delay t ba - 14.5 - 11 ns avd setup time to clk t avds 5-5-ns avd hold time from clk t avdh 7-6-ns avd high to oe low t avdo 0-0-ns address setup time to clk t acs 5-5-ns address hold time from clk t ach 7-6-ns data hold time from next clock cycle t bdh 4-4-ns output enable to data t oe - 20 - 20 ns output enable to rdy valid t oer - 14.5 - 11 ns ce disable to high z t cez - 20 - 20 ns oe disable to high z t oez - 15 - 15 ns ce setup time to clk t ces 7-6-ns clk to rdy setup time t rdya - 14.5 - 11 ns rdy setup time to clk t rdys 4-4-ns clk high or low time t clkh/l 4.5 - 3.5 - ns clk fall or rise time t clkhcl -3-3ns
flash memory k8s6415et(b)b revision 1.1 january, 2006 23 switching waveforms t ces t avds t avdh t acs t ach t iaa t oer t ba t bdh t cez t oez hi-z hi-z hi-z da da+1 da+2 da+n ce clk avd oe a/dq0: a/dq15 rdy aa aa figure 3. continuous burst mode read (66 mhz) a16-a21 da+3 note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. t rdys t ces t avds t avdh t acs t ach t iaa t oer t ba t bdh t cez t oez 18.5ns typ. hi-z hi-z hi-z da da+1 da+2 da+n ce clk avd oe a/dq0: a/dq15 rdy aa aa figure 4. continuous bu rst mode read (54 mhz) a16-a21 da+3 note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. t rdys 5 cycles for initial access shown. cr setting : a14=0, a13=0, a12=1 4 cycles for initial access shown. cr setting : a14=0, a13=0, a12=0 15.2 ns typ. t avdo t avdo t rdya t rdya
flash memory k8s6415et(b)b revision 1.1 january, 2006 24 t ces t avds t avdh t acs t ach t iaa t oer t ba t bdh hi-z d6 d7 d0 ce clk avd oe a/dq0: a/dq15 rdy aa aa figure 5. 8 word linear burst mode with wrap around (66 mhz) a16-a21 d1 note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. t rdys 5 cycles for initial access shown. cr setting : a14=0, a13=0, a12=1 15.2 ns typ.. d2 d3 d7 d0 switching waveforms t ces t avds t avdh t acs t ach t iaa t oer t ba t bdh hi-z d6 d7 d0 ce clk avd oe a/dq0: a/dq15 rdy aa aa a16-a21 d1 note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. t rdys 5 cycles for initial access shown. cr setting : a14=0, a13=0, a12=1 15.2 ns typ. d2 d3 d7 d0 figure 6. 8 word linear burst with rdy set one cycle before data (wrap around mode, cr setting : a18=1) t avdo t avdo t rdya t rdya
flash memory k8s6415et(b)b revision 1.1 january, 2006 25 t ces t avds t avdh t acs t ach t iaa t oer t ba t bdh t cez t oez hi-z hi-z hi-z ce clk avd oe a/dq0: a/dq15 rdy aa aa figure 7. 8 word linear burst mode (no wrap case) a16-a21 note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. t rdys 5 cycles for initial access shown. cr setting : a14=0, a13=0, a12=1 15.2ns typ d6 d7 d8 d9 d10 d13 switching waveforms t avdo t rdya
flash memory k8s6415et(b)b revision 1.1 january, 2006 26 ac characteristics switching waveforms t oe va va valid rd t ce t oeh t oez t aavdh t avdp t aavds ce oe we a/dq0: avd a/dq15 a16-a21 asynchronous mode read (tce) hi-z hi-z rdy asynchronous read note: 1. not 100% tested. parameter symbol 7b 7c unit min max min max access time from ce low t ce - 90 - 80 ns asynchronous access time t aa - 90 - 80 ns avd low time t avdp 12 - 12 - ns address setup time to rising edge of avd t aavds 5-5-ns address hold time from rising edge of avd t aavdh 7-7-ns output enable to output valid t oe - 20 - 20 ns output enable hold time read t oeh 0-0-ns toggle and data polling 10 - 10 - ns output disable to high z(note 1) t oez - 15 - 15 ns
flash memory k8s6415et(b)b revision 1.1 january, 2006 27 t oe va va valid rd t oeh t oez t aa t aavdh t avdp t aavds ce oe we a/dq0: avd a/dq15 a16-a21 t oe va va valid rd t oeh t oez t aa t aavdh t avdp t aavds ce oe we a/dq0: avd a/dq15 a16-a21 figure 8. asynchronous mode read note: va=valid read address, rd=read data. asynchronous mode read (taa) case 1 : valid address transition occurs before avd is driven to low case 2 : valid address transition occurs after avd is driven to low hi-z hi-z rdy hi-z hi-z rdy
flash memory k8s6415et(b)b revision 1.1 january, 2006 28 ac characteristics figure 9. reset timings t rh ce , oe reset t rp t ready t ready ce , oe reset t rp reset timings not during internal routines reset timings during internal routines hardware reset(reset ) note: not 100% tested. parameter symbol all speed options unit min max reset pin low(during internal routines) to read mode (note) t ready -20 s reset pin low(not during internal routines) to read mode (note) t ready - 500 ns reset pulse width t rp 200 - ns reset high time before read (note) t rh 200 - ns reset low to standby mode t rpd 20 - s switching waveforms
flash memory k8s6415et(b)b revision 1.1 january, 2006 29 erase/program operation notes: 1. not 100% tested. 2. not include the preprogramming time. parameter symbol 7b, 7c unit min typ max we cycle time(note 1) t wc 100 - - ns address setup time t as 5--ns address hold time t ah 7--ns avd low time t avdp 12 - - ns data setup time t ds 50 - - ns data hold time t dh 0--ns read recovery time before write t ghwl -0-ns ce setup time t cs -0-ns ce hold time t ch -0-ns we disable to avd enable t wea 30 - - ns we pulse width t wp -60-ns we pulse width high t wph -40-ns latency between read and write operations t sr/w 0--ns word programming operation t pgm -11.5- s accelerated single word programming operation t accpgm -6.5- s accelerated quad word programming operation t accpgm_quad -6.5- s main block erase operation (note 2) t bers -0.7-sec v pp rise and fall time t vpp 500 - - ns v pp setup time (during accelerated programming) t vps 1-- s v cc setup time t vcs 50 - - s ac characteristics flash erase/program performance notes: 1. 25 c, v cc = 1.8v, 100,000 cycles, typical pattern. 2. system-level overhead is defined as the time required to execute the two or fo ur bus cycle command necessary to program each word. in the preprogramming step of the internal erase routine, all words are programmed to 00h before erasure. 3. 100k program/erase cycle in all bank parameter limits unit comments min. typ. max. block erase time 32 kword - 0.7 14 sec excludes 00h programming prior to erasure 4 kword - 0.2 4 chip erase time - 91 - accelerated chip erase time - 60 - word programming time - 11.5 210 s excludes system level overhead accelerated single word programming time - 6.5 120 accelerated quad word programming time - 6.5 120 chip programming time - 46 - sec accelerated singl word chip programming time - 26 - accelerated quad word chip programming time - 6 - erase/program endurance (note 3) 100,000 - - cycles minimum 100,000 cycles guaran- teed in all bank
flash memory k8s6415et(b)b revision 1.1 january, 2006 30 program command sequence (last two cycles) avd a16:a21 we ce clk t avdp t as t ah t ds t dh t ch t wp t cs t wph t wc t pgm t vcs pa va va va va in progress complete pd pa a0h 555h a/dq0: a/dq15 oe v cc read status data notes: 1. pa = program address, pd = program data , va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a16?a21 are don?t care dur ing command sequence unlock cycles. 4. status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. figure 10. program operation timing switching waveforms v il program operations t wea
flash memory k8s6415et(b)b revision 1.1 january, 2006 31 erase command sequence (last two cycles) avd a16:a21 we ce t avdp t as t ah t ds t dh t ch t bers t vcs ba va va va va in progress complete 30h ba 55h 2aah a/dq0: a/dq15 oe v cc read status data notes: 1. ba is the block address for block erase. 2. address bits a16?a21 are don?t cares duri ng unlock cycles in the command sequence. 3. status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. figure 11. chlp/block erase operations switching waveforms 555h for chip erase 10h for chip erase t wp t cs t wph t wc clk v il erase operation t wea
flash memory k8s6415et(b)b revision 1.1 january, 2006 32 switching waveforms figure 12. unlock bypass operation timings ce avd oe a16:a21 v pp we a/dq0: a/dq15 1us t vps v il or v ih v id t vpp pa pa don?t care a0h pd don?t care ce avd oe a16:a21 v pp we a/dq0: a/dq15 1us t vps v il or v ih v id t vpp ba ba don?t care 80h 30h don?t care 555h for chip erase 10h for chip erase unlock bypass program operations(accelerated program) unlock bypass block erase operations notes: 1. v pp can be left high for subsequent programming pulses. 2. use setup and hold times from conventional program operations. 3. unlock bypass program/erase commands can be used when the v id is applied to vpp.
flash memory k8s6415et(b)b revision 1.1 january, 2006 33 figure 13. quad word accelerated program operation timings ce avd oe a16:a21 v pp we a/dq0: a/dq15 1us t vps v il or v ih v id t vpp don?t care quad word accelerated program notes: 1. v pp can be left high for subsequent programming pulses. 2. use setup and hold times from c onventional program operations. 3. quad word acelerate program commands can be used when the v id is applied to vpp. switching waveforms t accpgm_quad a5h pa1 pa1 pd1 pa2 pa2 pd2 pa3 pa3 pd3 pa4 pa4 pd4 don?t care va va complete
flash memory k8s6415et(b)b revision 1.1 january, 2006 34 switching waveforms notes: 1. va = valid address. when the internal routine operation is complete, and data polling will output true data. figure 14. flash data polling timings (during internal routine) notes: 1. va = valid address. when the internal routine operation is complete, the toggle bits will stop toggling. figure 15. toggle bit timings(duri ng internal routine) data polling operations toggle bit operations t ces t avds t avdh t acs t ach t iaa hi-z ce clk avd oe a/dq0: a/dq15 rdy va va a16-a21 t rdys status data toggle status data t ces t avds t avdh t acs t ach t iaa hi-z ce clk avd oe a/dq0: a/dq15 rdy va va a16-a21 t rdys status data va va status data t oe
flash memory k8s6415et(b)b revision 1.1 january, 2006 35 switching waveforms t wc ce oe we a/dq0: avd a/dq15 a16-a21 note: breakpoints in waveforms indicate that system may alternatel y read array data from the ?non-busy bank? and checking the status of the program or erase operation in the ?busy? bank. figure 16. read while write operation pa/ba pd/30h ra ra 555h aah pa/ba ra ra rd rd last cycle in program or block erase command sequence read status in same bank and/or array data from other bank t rc t rc t wc t oe t oeh t wph t wp t aa t oeh t ds t dh t sr/w t as t ah t ghwl command sequences read while write operations program or erase begin another
flash memory k8s6415et(b)b revision 1.1 january, 2006 36 crossing of first word boundary in burst read mode starting address vs. additional cl ock cycles for fi rst word boundary srarting address group for burst read the residue of (address/4) lsb bits of address additional clock cycles for first word boundary crossing 4n 0 00 0 cycle 4n+1 1 01 1 cycle 4n+2 2 10 2 cycles 4n+3 3 11 3 cycles the additional clock insertion for word boundary is needed only at the first crossing of word boundary. this means that no addt ional clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. also, the number of addtional clock cycle for the first word boundary can varies from zero to three cyc les, and the exact number of addi tional clock cy cle depends on the start- ing address of burst read. the rule to determine the additional clock cycle is as follows . all addresses can be divided into 4 groups. the applied rule is "the res- idue obtained when the address is divided by 4" or "two lsb bits of address". using this rule, all address can be divided by 4 different groups as shown in below table. for simplicity of terminology, "4n" stands for the address of which the residue is "0"(or the t wo lsb bits are "00") and "4n+1" for the address of which the residue is "1"(or the two lsb bits are "01"), etc. the additional clock cy cles for first word boundary crossing are zero, one, tw o or three when the burst read start from "4n" ad dress, "4n+1" address, "4n+2" address or "4n+3" address respectively. notes: 1. address boundry occurs every 16 words beginning at address 00003fh , 00007fh , 0000bfh , etc. 2. address 000000h is also a boundry crossing. 3. no additional clock cycles are needed except for 1st boundary crossing. figure 17. flash crossing of first word boundary in burst read mode. case 1 : start from "4n" address group ce oe rdy clk address/ data bus avd t cez t oez t oer valid address 3d 414243 40 3c 3d 41 42 43 44 no additional cycle for first word boundary 5 cycle for initial access shown.(66mhz case) programmable wait state function is set to 01h (wait states 3) 3e 3c 3e 3f 3f 40
flash memory k8s6415et(b)b revision 1.1 january, 2006 37 notes: 1. address boundry occurs every 16 words beginning at address 00003fh , 00007fh , 0000bfh , etc. 2. address 000000h is also a boundry crossing. 3. no additional clock cycles ar e needed except for 1st boundary crossing. figure 18. flash crossing of first word boundary in burst read mode. case 3 : start from "4n+2" address group ce oe rdy clk address/ data bus avd t cez t oez t oer valid address 3f 41 42 43 40 3d 3e 41 42 43 44 additional 1 cycle for first word boundary 5 cycle for initial access shown.(66mhz case) programmable wait state function is set to 01h (wait states 3) 3e 3d 3f 40 case2 : start from "4n+1" address group ce oe rdy clk address/ data bus avd t cez t oez t oer valid address 3f 414243 40 3e 3f 41 42 43 44 additional 2 cycle for first word boundary 5 cycle for initial access shown.(66mhz case) programmable wait state function is set to 01h (wait states 3) 40 3e
flash memory k8s6415et(b)b revision 1.1 january, 2006 38 notes: 1. address boundry occurs every 16 words beginning at address 00003fh , 00007fh , 0000bfh , etc. 2. address 000000h is also a boundry crossing. 3. no additional clock cycles ar e needed except for 1st boundary crossing. figure 19. crossing of first word boundary in burst read mode. case4 : start from "4n+3" address group ce oe rdy clk address/ data bus avd t cez t oez t oer valid address 3f 41 42 43 40 3f 40 41 42 43 44 additional 3 cycle for first word boundary 5 cycle for initial access shown.(66mhz case) programmable wait state function is set to 01h (wait states 3)
flash memory k8s6415et(b)b revision 1.1 january, 2006 39 package dimensions 44-ball fine ball grid array package 0.50x3=1.50 b 44- ? 0.30 0.05 0.2 m a b ? (datum a) (datum b) 7.50 0.10 a 1.00 3.25 1.00 1.75 8.50 0.10 7.50 0.10 #a1 0.50 0.50 1 3 52 4 6 7 8 9 10 #a1 index mark 0.30 0.05 bottom view top view 8.50 0.10 0.50x9=4.50 a b d c 8.50 0.10 0.20 0.05 0.90 0.10 0.08 max

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